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- #Connecting dsp builder modules serial
- #Connecting dsp builder modules portable
- #Connecting dsp builder modules software
- #Connecting dsp builder modules code
So when interfacing to the co-processor the DMA controller is used. Today, high performance DSP processors rely on DMA controllers to minimize CPU overhead when moving data. When the processor communicates with the co-processor, the efficiency of data movement often becomes the dominant factor in the overall system performance. For this example system, the EMIF interface is used because it is common to all the C6X devices, its flexibility and high performance ( >=200MHz).
#Connecting dsp builder modules serial
For example, the TI C6X DSPs support several interfaces such as External Memory InterFace (EMIF), Host-Port Interface, and the Multi-Channel Buffered Serial Ports (McBSPs). The interface selection between the processor and the FPGA is driven by the application characteristics as well as the available interfaces on the processor.
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2 Modem Co-Processor Captured in DSP Builder In this case, DSP Builder has been used to assemble the design from the Altera blockset of DSP Builder including the FIR and NCO MegaCore functions. The co-processing block identified in the modem.c example requires the integration of a FIR filter, a modulator, and two look-up tables. One of the features of DSP Builder is the ability package these dataflow systems into co-processing blocks. The building blocks of DSP Builder include modular RTL building blocks and optional parameterized complex IP building blocks. DSP Builder is an add-on tool to the Mathworks MATLAB and Simulink toolset and provides an integrated design environment for dataflow system design, verification, and implementation for Altera FPGAs enabling designers to assemble parameterized building blocks into complex data flow processing systems. There are several mechanisms available to build co-processors including standard HDL flows as well as methods such as Altera’s DSP Builder.
#Connecting dsp builder modules code
1: TI Modem.c Structure and Code Profile Results The content of the modem_tx includes a RRC shaping filter (82% MIPS), modulation (8% MIPS), sine lookup (2.5% MIPS) and the cosine lookup (3.5% MIPS). The modem_tx is also very suitable for off-loading to an FPGA co-processor.
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The analysis shows that the majority of the processing is consumed by the modem transmitter algorithm modem_tx, taking 96.5% of the total processing MIPS. TI’s Code Composer Studio (CCS) is then used to profile the Modem.c example to identify what could be off-loaded to a FPGA Co-processor.
#Connecting dsp builder modules software
Modem.c implements a 16 QAM modem entirely in software and when modem.c is compiled and executed on the TI C6711 development system, it takes 177,000 instruction cycles to execute. The example system discussed uses one of the application examples, modem.c which comes with the TI development kits. With code profiling, the functions that consume the majority of the MIPS can be identified and the option to be accelerated by a HARDWARE co-processor can be made. The key to identify what should be offloaded is the profiling tool used by the software developer. The challenge is to identify what should be offloaded from the DSP to a coprocessor. This creates a double challenge for DSP software engineers, reducing the processing load in 20% of the software and managing the complexity of the remaining 80% of the code.įPGA co-processing is well suited to addressing that 80% processing load caused by 20% of the algorithm code.
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At the same time, the other 80% of the code reflects the majority of the system complexity.
#Connecting dsp builder modules portable
This code also becomes far less portable than the remaining 80% of the code, which is focused on initialization and system execution control. This 20% of the program code requires time consuming, error prone, and difficult to maintain assembly coding to increase overall system performance. Often in DSP processing applications, 80% of the MIPS required are consumed by 20% of the program code. In applications where no co-processors are available, Altera is developing design tools and methodologies that enable companies to develop their own coprocessors using Altera’s Stratix and Cyclone devices that easily interface with a wide range of DSP and general purpose processors (GPP), providing increased system performance and lower system costs. In a few cases, DSP processors include some on-chip hardware coprocessors where the end application supports the expense of designing a market specific solution. In some of these applications, software developers have used hardware co-processors to off-load a variety of algorithms including Viterbi decoding and FIR filters. Across a wide spectrum of applications, the growth in signal processing algorithm complexity is exceeding the processing capabilities of stand-alone digital signal processors.